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november 2015 docid028296 rev 1 1 / 19 this is information on a product in full production. www.st.com LDBL20 200 ma very low quiescent current linear regulator ic in (0.47x0.47) mm2 ststamp? package datasheet - production data features ? input voltage from 1.5 to 5.5 v ? ultra low - dropout voltage (200 mv typ. at 200 ma load) ? very low quiescent current (20 a typ. at no - load, 0.03 a typ. in off mode) ? output voltage tolerance: 1.5% @ 25 c ? 200 ma guaranteed output current ? high psrr (80 db@1 khz, 50 db@100 khz) ? wide range of output voltages available on request: from 0.8 v up to 5.0 v in 50 mv step ? logic - controlled electronic shutdown ? internal soft - start ? optional output voltage discharge feature ? compatible with ceramic capacitor c out = 0.47 f ? internal constant current and thermal protections ? available in ststamp? (0.47x0.47 ) mm2 package ? operating temperature range: - 40 c to 125 c application ? mobile phones ? tablet ? digital still cameras (dsc) ? wearable devices ? portable media players description the LDBL20 high accuracy voltage regulator provides 200 ma of maximum current from an input voltage ranging from 1.5 v to 5.5 v, with a typical dropout voltage of 200 mv. it is ava ilable in the new ststamp? package, allowing the maximum space saving. the device is stabilized with a ceramic capacitor on the output. the ultra low drop voltage, low quiescent current and low noise features, together with the internal soft - start circuit, make the LDBL20 suitable for low power battery - operated applications. an enable logic control function puts the LDBL20 in shutdown mode with a total current consumption lower than 0.2 a. constant current and thermal protection are provided.
contents LDBL20 2 / 19 docid028296 rev 1 contents 1 diagram ................................ ................................ ............................ 3 2 pin configuration ................................ ................................ ............. 4 3 typ ical application ................................ ................................ .......... 5 4 maximum ratings ................................ ................................ ............ 6 5 electrical characteristics ................................ ................................ 7 6 application information ................................ ................................ .. 9 6.1 soft - start function ................................ ................................ .............. 9 6.2 output discharge function ................................ ................................ . 9 6.3 input output capacitors ................................ ................................ ...... 9 7 typical characteristics ................................ ................................ .. 10 8 package information ................................ ................................ ..... 14 8.1 ststamp? (0.47x0.47) mm2 package information ....................... 15 9 ordering information ................................ ................................ ..... 17 10 revision history ................................ ................................ ............ 18
LDBL20 diagram docid028296 rev 1 3 / 19 1 diagram figure 1 : block diagram the output discharge mosfet is optional.
pin configuration LDBL20 4 / 19 docid028296 rev 1 2 pin configuration figure 2 : pin connection table 1: pin description pin symbol function 3 out output voltage 4 gnd common ground 1 en enable pin logic input: low = shutdown, high = active 2 in input voltage 3 4 2 1 v i n v o u t en g n d b o tt o m v i e w 3 4 2 1 v i n v o u t en g n d marking v i e w gipd310820151050mt
LDBL20 typical application docid028296 rev 1 5 / 19 3 typical application figure 3 : typical application circuits v i n g n d v i e n c i n v o v o u t c o u t l d b l 2 0 o ff o n gipd31082015 11 19m t
maximum ratings LDBL20 6 / 19 docid028296 rev 1 4 maximum ratings table 2: absolute maximum ratings symbol parameter value unit v in input voltage - 0.3 to 7 v v out output voltage - 0.3 to v in + 0.3 v v en enable input voltage - 0.3 to 7 v i out output current internally limited ma p d power dissipation internally limited mw t stg storage temperature range - 40 to 150 c t op operating junction temperature range - 40 to 125 c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. all values are referred to gnd. table 3: esd performance symbol parameter test conditions value unit esd esd protection voltage hbm 4 kv mm 400 v cdm 500 v
LDBL20 electrical characteristics docid028296 rev 1 7 / 19 5 electrical characteristics t j = 25 c, v in = v out(nom) + 1 v or 1.5 v, whichever is greater, c in = c out = 1 f, i out = 1 ma, v en = v in , unless otherwise specified. table 4: LDBL20 electrical characteristics symbol parameter test conditions min. typ. max. unit v in operating input voltage 1.5 5.5 v v out v out accuracy i out = 1 ma, t j = 25 c - 1.5 +1.5 % i out = 1 ma, - 40 c electrical characteristics LDBL20 8 / 19 docid028296 rev 1 symbol parameter test conditions min. typ. max. unit t shdn thermal shutdown 160 c hysteresis 20 c out output capacitor capacitance 0.47 22 f notes: (1) not applicable for vout(nom) > 4.5 v (2) turn - on time is time measured between the enable input just exceeding ven high value and the output voltage just reaching 95 % of its nominal value
LDBL20 application information docid028296 rev 1 9 / 19 6 application information 6.1 soft - start function the LDBL20 has an internal soft - start circuit. by increasing the startup time up to 100 s, without the need of any external soft - start capacitor, this feature keeps the regulator inrush current at startup under control. 6.2 output discharge function the LDBL20 integrates a mosfet connected between v out and gnd. th is transistor is activated when the en pin goes to low logic level and has the function to quickly discharge the output capacitor when the device is disabled by the user. the device is available with or without the auto - discharge feature. see table 6: "order code" . 6.3 input output capacitors the LDBL20 requires external capacitors to assure the regulator control loop stability. an y good quality ceramic capacitor can be used but, the x5r and the x7r are suggested since they guarantee a very stable combination of capacitance and esr overtemperature. locating the input/output capacitors as closer as possible to the relative pins is re commended. the LDBL20 requires an input capacitor with a minimum value of 1 f. this capacitor must be located as closer as possible to the input pin of the device and returned to a clean analog ground. the control loop of the LDBL20 is designed to work w ith an output ceramic capacitor. this capacitor must meet the requirements of minimum capacitance and equivalent series resistance (esr), as shown in figure 17: "stability area vs (cout, esr)" . to assure stability, the outp ut capacitor must maintain its esr and capacitance in the stable region, over the full operating temperature range. the LDBL20 shows stability with a minimum effective output capacitance of 220 nf. however, to keep stability in all operating conditions (te mperature, input voltage and load variations), a minimum output capacitor of 0.47 f is recommended. the suggested combination of 1 f input and output capacitors offers a good compromise among the stability of the regulator, optimum transient response an d total pcb area occupation.
typical characte ristics LDBL20 10 / 19 docid028296 rev 1 7 typical characteristics (c in = c out = 1 f, v en to v in, t j = 25 c unless otherwise specified) figure 4 : output voltage vs temperature (i out = 1 ma) figure 5 : output voltage vs temperature (i out = 200 ma) figure 6 : line regulation vs temperature figure 7 : load regulation vs temperature figure 8 : quiescent current vs temperature (i out = 0 ma) figure 9 : quiescent current vs temperature (i out = 200 ma) load regulation
LDBL20 typical characteristics docid028296 rev 1 11 / 19 figure 10 : shutdown current vs temperature figure 11 : quiescent current vs load current figure 12 : quiescent current vs input voltage figure 13 : dropout voltage vs temperature figure 14 : supply voltage rejection vs frequency figure 15 : supply voltage rejection vs input voltage
typical characteristics LDBL20 12 / 19 docid028296 rev 1 figure 16 : output noise spectral density figure 17 : stability area vs (c out , esr) figure 18 : enable startup (v out = 1 v) figure 19 : enable startup (v out = 5 v) figure 20 : turn - on time (v out = 1 v) figure 21 : turn - off time (v o ut = 1 v)
LDBL20 typical characteristics docid028296 rev 1 13 / 19 figure 22 : turn - on time (v out = 5 v) figure 23 : turn - off time (v out = 5 v) figure 24 : line transient (v out = 1 v) figure 25 : line transient (v out = 5 v) figure 26 : load transient (v out = 1 v) figure 27 : load transient (v out = 5 v)
package information LDBL20 14 / 19 docid028296 rev 1 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? speci fications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
LDBL20 package information docid028296 rev 1 15 / 19 8.1 ststamp? (0.47x0.47) mm2 package information figure 28 : ststamp? (0.47x0.47) mm2 package outline
package information LDBL20 16 / 19 docid028296 rev 1 table 5: ststamp? (0.47x0.47) mm2 mechanical data dim. mm min. typ. max. a 0.18 0.200 0.220 b 0.060 0.065 0.070 b1 0.109 0.114 0.119 e 0.450 0.480 0.510 e1 0.208 0.213 0.218 e2 0.019 0.024 0.029 e3 0.034 0.039 0.044 d 0.450 0.480 0.510 d1 0.252 0.257 0.262 d2 0.255 0.260 0.265 fe 0.095 0.101 0.106 fd 0.106 0.111 0.116 figure 29 : ststamp? (0.47x0.47) mm2 recommended footprint figure 30 : ststamp? (0.47x0.47) mm2 recommended solder stencil 180 m 180 m 120 m 180 m 180 m 120 m 0.25 0.25 0.1 0.25 0.25 0.1
LDBL20 ordering information docid028296 rev 1 17 / 19 9 order ing information table 6: order code order code output voltage (v) auto - discharge packing LDBL20d - xyr x.y yes tape and reel
revision history LDBL20 18 / 19 docid028296 rev 1 10 revision history table 7: document revision history date revision changes 10 - nov - 2015 1 initial release
LDBL20 docid028296 rev 1 19 / 19 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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